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HCF40100B
32-STAGE STATIC LEFT/RIGHT SHIFT REGISTER
s s s s s s
s s s
s s
FULLY STATIC OPERATION SHIFT LEFT/SHIFT RIGHT CAPABILITY MULTIPLE PACKAGE CASCADING RECIRCULATE CAPABILITY LIFO OR FIFO CAPABILITY STANDARDIZED SYMMETRICAL OUTPUT CHARACTERISTICS QUIESCENT CURRENT SPECIF. UP TO 20V 5V, 10V AND 15V PARAMETRIC RATINGS INPUT LEAKAGE CURRENT II = 100nA (MAX) AT VDD = 18V TA = 25C 100% TESTED FOR QUIESCENT CURRENT MEETS ALL REQUIREMENTS OF JEDEC JESD13B "STANDARD SPECIFICATIONS FOR DESCRIPTION OF B SERIES CMOS DEVICES"
DIP
SOP
ORDER CODES
PACKAGE DIP SOP TUBE HCF40100BEY HCF40100BM1 T&R HCF40100M013TR
DESCRIPTION HCF40100B is a monolithic integrated circuit fabricated in Metal Oxide Semiconductor technology available in DIP and SOP packages. HCF40100B is a 32-stage shift register containing 32 D-Type master slave flip-flops. The data present at the SHIFT RIGHT INPUT is synchronously transferred into the first register stage with the positive CLOCK edge, provided the LEFT/RIGHT CONTROL is at a low level, the RECIRCULATE CONTROL is at a high level, and the CLOCK INHIBIT is low. If the LEFT/RIGHT control and the RECIRCULATE CONTROL are both at a high level, data at the SHIFT LEFT INPUT is synchronously transferred into the 32nd PIN CONNECTION
register stage with the positive CLOCK transition, provided the CLOCK INHIBIT is low. The state of the LEFT/RIGHT CONTROL, RECIRCULATE CONTROL, and CLOCK INHIBIT should not be changed when the CLOCK is high. Data is synchronously shifted one stage left or one stage right depending on the state of the LEFT/RIGHT CONTROL, with the positive CLOCK edge. Data clocked into the first of 32 register states is available at the SHIFT LEFT or SHIFT RIGHT OUTPUT respectively, on the next negative CLOCK transition (see Data Transfer Table). No shifting occurs on the positive CLOCK edge if the CLOCK INHIBIT line is at a high level. With the RECIRCULATE CONTROL low, data in the 32nd stage is shifted into the first stage when the LEFT/ RIGHT CONTROL is low and from the 1st stage to the 32nd stage when the LEFT/RIGHT CONTROL is high.
September 2002
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HCF40100B
IINPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN No 11 6 12 4 3 2 13 9 1, 5, 7, 10, 14, 15 8 16 SYMBOL SHIFT RIGHT IN SHIFT LEFT IN SHIFT RIGHT OUT SHIFT LEFT OUT CLOCK CLOCK INHIBIT LEFT/RIGHT CONTROL RECIRCULATE CONTROL NC VSS VDD NAME AND FUNCTION Shift Right In Shift Left In Shift Right Out Shift Left Out Clock Clock Inhibit Left/Right Control Recirculate Control Not Connected Negative Supply Voltage Positive Supply Voltage
FUNCTIONAL DIAGRAM
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HCF40100B
TRUTH TABLES CONTROL
Left/Right Control H H L L X Clock Inhibit L L L L H Recirculate Control H L H L X Action Shift Left Shift Left Shift Right Shift Right No Shift Input Bit Origin Shift Left Input Stage 1 Shift Right Input Stage 32 -
DATA TRANSFER
INITIAL STATE Data Input L X H X X Clock Inhibit L L L L H Internal Stage X L X H H X CLOCK Level Change Resulting State Internal Stage Q L NC H NC NC Output NC L NC H NC
X : Don't Care NC : No Change For Shift-Right Mode: Data Input = SHIFT RIGHT INPUT (Pin 11); Internal Stage = Stage1 (Q1); Output = SHIFT LEFT OUTPUT (Pin 4) . For Shift-Left Mode: Data Input = SHIFT LEFT INPUT (Pin 6); Internal Stage = Stage32 (Q32); Output = SHIFT RIGHT OUTPUT (Pin 12).
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HCF40100B
LOGIC DIAGRAM
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HCF40100B
ABSOLUTE MAXIMUM RATINGS
Symbol VDD VI II PD Top Tstg Supply Voltage DC Input Voltage DC Input Current Power Dissipation per Package Power Dissipation per Output Transistor Operating Temperature Storage Temperature Parameter Value -0.5 to +22 -0.5 to VDD + 0.5 10 200 100 -55 to +125 -65 to +150 Unit V V mA mW mW C C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. All voltage values are referred to VSS pin voltage.
RECOMMENDED OPERATING CONDITIONS
Symbol VDD VI Top Supply Voltage Input Voltage Operating Temperature Parameter Value 3 to 20 0 to VDD -55 to 125 Unit V V C
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HCF40100B
DC SPECIFICATIONS
Test Condition Symbol Parameter VI (V) 0/5 0/10 0/15 0/20 0/5 0/10 0/15 5/0 10/0 15/0 0.5/4.5 1/9 1.5/13.5 4.5/0.5 9/1 13.5/1.5 2.5 4.6 9.5 13.5 0.4 0.5 1.5 VO (V) |IO| VDD (A) (V) 5 10 15 20 5 10 15 5 10 15 5 10 15 5 10 15 5 5 10 15 5 10 15 18 TA = 25C Min. Typ. 0.04 0.04 0.04 0.08 4.95 9.95 14.95 0.05 0.05 0.05 3.5 7 11 1.5 3 4 -1.36 -0.44 -1.1 -3.0 0.44 1.1 3.0 -3.2 -1 -2.6 -6.8 1 2.6 6.8 10-5 5 -1.1 -0.36 -0.9 -2.4 0.36 0.9 2.4 3.5 7 11 1.5 3 4 -1.1 -0.36 -0.9 -2.4 0.36 0.9 2.4 Max. 5 10 20 100 4.95 9.95 14.95 0.05 0.05 0.05 3.5 7 11 1.5 3 4 Value -40 to 85C Min. Max. 150 300 600 3000 4.95 9.95 14.95 0.05 0.05 0.05 -55 to 125C Min. Max. 150 300 600 3000 Unit
IL
Quiescent Current
A
VOH
High Level Output Voltage Low Level Output Voltage High Level Input Voltage Low Level Input Voltage Output Drive Current
VOL
VIH
VIL
IOH
IOL
Output Sink Current Input Leakage Current Input Capacitance
0/5 0/5 0/10 0/15 0/5 0/10 0/15 0/18
<1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1
V
V
V
V
mA
mA
II
Any Input Any Input
0.1
7.5
1
1
A
pF
CI
The Noise Margin for both "1" and "0" level is: 1V min. with VDD =5V, 2V min. with VDD=10V, 2.5V min. with VDD=15V
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HCF40100B
DYNAMIC ELECTRICAL CHARACTERISTICS (Tamb = 25C, CL = 50pF, RL = 200K, tr = tf = 20 ns)
Test Condition Symbol Parameter VDD (V) 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 Min. Value (*) Typ. 360 165 115 100 50 40 50 10 5 170 75 50 225 115 95 140 75 70 2 5 6 Max. 720 330 230 200 100 80 ns Unit
tPLH tPHL Propagation Delay Time
tTHL tTLH Transition Time
ns
tsetup
Data Setup Time
thold
Data Hold Time
tW
Clock Input Pulse Width Low Level Clock Input Pulse Width High Level Maximum Clock Input Frequency
tW
fCL
100 20 10 275 100 75 450 230 190 280 150 140 1 2.5 3
ns
ns
ns
ns
MHz
(*) Typical temperature coefficient for all VDD value is 0.3 %/C.
TEST CIRCUIT
CL = 50pF or equivalent (includes jig and probe capacitance) RL = 200K RT = ZOUT of pulse generator (typically 50)
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HCF40100B
WAVEFORM : PROPAGATION DELAY, DATA SETUP, TIME, CLOCK PULSE WIDTH (f=1MHz; 50% duty cycle)
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HCF40100B
Plastic DIP-16 (0.25) MECHANICAL DATA
mm. DIM. MIN. a1 B b b1 D E e e3 F I L Z 3.3 1.27 8.5 2.54 17.78 7.1 5.1 0.130 0.050 0.51 0.77 0.5 0.25 20 0.335 0.100 0.700 0.280 0.201 1.65 TYP MAX. MIN. 0.020 0.030 0.020 0.010 0.787 0.065 TYP. MAX. inch
P001C
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HCF40100B
SO-16 MECHANICAL DATA
DIM. A a1 a2 b b1 C c1 D E e e3 F G L M S 3.8 4.6 0.5 9.8 5.8 1.27 8.89 4.0 5.3 1.27 0.62 8 (max.) 0.149 0.181 0.019 10 6.2 0.35 0.19 0.5 45 (typ.) 0.385 0.228 0.050 0.350 0.157 0.208 0.050 0.024 0.393 0.244 0.1 mm. MIN. TYP MAX. 1.75 0.2 1.65 0.46 0.25 0.013 0.007 0.019 0.003 MIN. inch TYP. MAX. 0.068 0.007 0.064 0.018 0.010
PO13H
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HCF40100B
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. (c) The ST logo is a registered trademark of STMicroelectronics (c) 2002 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. (c) http://www.st.com
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